In power electronics devices including a pn-junction, substrates having a thickness larger than a maximum thickness of a depletion layer in reverse operation have been used. Thus, even at a maximum reverse voltage (i.e., slightly below a breakdown voltage of the device), the depletion layer and the electrical field prevailing therein do not reach to a collector of the device. Such devices are also referred to as non-punch-through devices (NPT).
However, it has been observed that electrical losses in electronic power devices strongly depend upon the thickness of the device. Accordingly, devices with reduced thickness have been developed.
In U.S. Pat. No. 6,762,080 B2 a punch-through (PT) insulated gate bipolar transistor (IGBT) is described. A doping concentration profile and a representation of an electrical field in such a PT-IGBT is schematically shown in FIG. 1. The device may be produced by using an n-doped wafer having a homogeneous doping concentration for forming a base layer 4. On top of the wafer all processes for manufacturing layers on an emitter side 31, also called cathode side, are performed (e.g., junctions and metallizations on the emitter side 31 are produced). The wafer further includes a deep highly doped n-type region opposite to the emitter side 31 for forming later, after thinning, a buffer layer 15. Afterwards, the wafer is thinned to the desired thickness leaving a buffer layer 15 on the collector side 21 of the wafer, which is opposite to the emitter side 31 and which is also called anode side. Then p-type particles are implanted on the collector side 21 of the wafer for forming a collector layer 6. The wafer is then annealed at 350° C. to 500° C. in order to activate the p-type particles without damage to the structure on the emitter side 31.
Due to the continuously rising doping concentration in the buffer layer 15 the reduction of the electric field during operation of the device increases within the buffer layer 15. Thus, the buffer layer 15 serves, in the blocking case, for decelerating the electric field (shown in FIG. 1 by the dotted line) before reaching the collector and thus keeping it away from said collector, since the semiconductor device can be destroyed if the electric field reaches the collector. The buffer layer can, for example, have a thickness in a range of 25 μm to 50 μm. Such devices may show reduced electrical losses. Due to the effect of the buffer layer 15, such devices are also referred to as soft-punch-through (SPT) devices.
Other devices with known doping concentration and thicknesses for the base layer and buffer layer are known from US 2009/0008674 A1, US 2008/0315248 A1 and US 2007/0096167 A1.
In U.S. Pat. No. 6,482,681 B1 an alternative punch-through (PT) IGBT is described. The device may be produced by using an n-doped wafer having a homogeneous doping concentration for forming a base layer 4, on top of which wafer all processes for manufacturing layers 10 on the emitter side 31, also called cathode side, are generated (e.g., junctions and metallizations on the emitter side 31 are produced). Afterwards, the wafer is thinned and hydrogen ions are implanted on the collector side 21 of the wafer, which is opposite to the emitter side 31 and which is also called anode side, for forming an n+-doped buffer layer 15. Then p-type particles are implanted for forming a collector layer 6. The wafer is then annealed at 350° C. to 450° C. in order to activate the p-type particles and hydrogen ions without damage to the structure on the emitter side 31. The buffer layer 15 can also be formed by multiple hydrogen implants of progressively shallower and progressively higher total dose in order to form one buffer layer 15 with increasing doping concentration towards the collector and a peak dose concentration close to the collector.
However, it has been observed that SPT semiconductor devices may not always provide desired electrical characteristics in specific applications.